Design & Reuse
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New Products

Truechip Solutions
eUSB2 v2 Verification IP
Dolphin Semiconductor
Linear Regulator for digital island in GF 22FDX
ARKCHIPS
TSMC RC Oscillator_RCOSC
Agile Analog
Electro-Magnetic Fault Injection (EMFI) Detector for Tamper Detection
T2M GmbH
ASA-ML Serdes IP Core in 22nm

Blogs

Root of Trust: A Security Essential for Cyber Defense
Vayavya Labs
Amit Shirodkar, Architect
Vayavya Labs
Introducing agileSecure anti-tamper security portfolio
Agile Analog
Chris Morrison, VP Product Marketing
Agile Analog
IntoPIX Launches Codec Plugin Pack For JPEG XS - FastTicoXS Now In GStreamer
intoPIX
Jean-Baptiste Lorent
intoPIX
Multiple ways JESD204 performs bitstream alignment
Chip Interfaces ApS
Piotr Koziuk
Chip Interfaces ApS
An Introduction to AMBA CHI Chip-to-Chip (C2C) Protocol
Cadence Design Systems, Inc.
Cadence Design Systems, Inc.
Customizing Foundation IP to Meet Low-Voltage Requirements
Synopsys, Inc.
Andrew Appleby, Daryl Seitzer, Mohammad Tanveer
Synopsys, Inc.
UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
Chip Interfaces ApS
Piotr Koziuk
Chip Interfaces ApS
Putting 3D IC to work for you
Siemens Digital Industries Software
Todd Burkholder and Tony Mastroianni
Siemens Digital Industries Software
Efficient IP Packaging for Today's SoC Integration
Arteris IP
Arteris IP
A point of view on ''Analog Design and Layout Migration automation in the AI era''
MosChip Technologies, USA
Khwaja Siddique Baig
MosChip Technologies, USA
Building Smarter, Faster: How Arm Compute Subsystems Accelerate the Future of Chip Design
Arm Inc.
Boost SoC Flexibility: 4 Design Tips for Memory Subsystems with Combo DDR3/4 Interfaces
Key ASIC
Key ASIC

Articles

AI in VLSI Physical Design: Opportunities and Challenges
Japesh Kumar, Qualcomm
AI-Driven and Traditional Approaches to Accident Scenario Reconstruction
Vayavya Labs
Nitin Swamy
Vayavya Labs
From Theory to the Field: Why Side-Channel Protection Defines Post-Quantum Security
PQSecure Technologies
PQSecure Technologies
PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
Innosilicon Technology Ltd
Innosilicon Technology Ltd
Design Approaches and Architectures of RISC-V SoCs
Maven Silicon
Maven Silicon
Implementation of Metal ECO using Mask Programmable Cell for Hold Timing Violations
eInfochips, Inc.
Dhanyakumar Shah,Dharmik Lakhani
eInfochips, Inc.
Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
Menta
Menta
Bridging Design Verification Gaps with Formal Verification
Karim Waseem, Si-vision
Post-Quantum Cryptography: Why Open Source alone is Not Enough for Secure IP Deployment
PQSecure Technologies
Dr. Reza Azarderakhsh
PQSecure Technologies
The Blind Spot of Semiconductor IP Sales
CoreHW
Petri Heliö, Principal IC Designer
CoreHW
SWE-Bench-C Evaluation Framework
Vayavya Labs
Vayavya Labs
Point of View: Key Recommendations for Enabling Predictive Maintenance at the Edge with AI in Industrial IoT
MosChip Technologies, USA
Nayan Goswami, Manager PES division
MosChip Technologies, USA
Asic Technology
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FPGA and eFPGA Corner
Select your target vendor and device
Today on Design And Reuse

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bullet_arrow  Weebit Nano tapes out embedded ReRAM test chips at onsemi production fab - October 6, 2025

bullet_arrow  Creonic Updates Doppler Channel IP Core with Extended Frequency Band and Sampling Range - October 6, 2025

bullet_arrow  QuickLogic Announces $1M eFPGA Hard IP Contract for Data Center ASIC - October 6, 2025

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