Design & Reuse
Partner Highlight

New Products

TES Electronic Solutions
10-bit SAR ADC
NTLab
130GF_EEPROM_08 - 3.6Kbit EEPROM IP with configuration 28p8w16bit
Dream Chip Technologies GmbH
Image Signal Processing, Real-time Pixel Processor Consumer
Global IP Core Sales
DVB-S2 Demodulator IP Core
Kamaten Technology Inc.
General Purpose Integer Hybrid PLL, CLN28HPC/HPC+, 80MHz - 8000MHz

Blogs

Maven Silicon & iHUB DivyaSampark, IIT Roorkee Collaboration
Maven Silicon
Maven Silicon
Physical AI at the Edge: A New Chapter in Device Intelligence
Ceva, Inc.
Iri Trashanski
Ceva, Inc.
The sixth sense of automotive safety: How radar is guiding the future of driving
Sneha Narnakaje
GlobalFoundries
Adapting Foundation IP to Exceed 2 nm Power Efficiency in Next-Gen Hyperscale Compute Engines
Synopsys, Inc.
Andrew Appleby, Daryl Seitzer
Synopsys, Inc.
UA Link PCS customizations from 800GBASE-R Ethernet PCS Clause 172
Chip Interfaces ApS
Piotr Koziuk
Chip Interfaces ApS
Inside GF’s decarbonization journey
Joseph Chia
GlobalFoundries
How Arm is redefining compute through the converged AI data center
Dermot O'Driscoll
Arm Inc.
RISC-V: The Open-Source Revolution in CPU Architecture
MosChip Technologies, USA
Darshil Shah
MosChip Technologies, USA
Light-speed ambition: GlobalFoundries acquires AMF and InfiniLink to power the AI datacenter revolution
Kevin Soukup
GlobalFoundries
How Time Sensitive Networking powers the Software Defined Vehicle
Comcores
Comcores
Maximizing SoC Longevity with PCIe 3.0: A Designer’s Guide
Key ASIC
Key ASIC
Key ASIC
Let's Visit the Zoo
Quadric
Quadric
Quadric

Articles

Security certification and the crucial role of anti-tamper sensor solutions
Agile Analog
Chris Morrison
Agile Analog
Beyond the Core: Tackling system-wide debugging for complex SoCs with Tessent UltraSight
Siemens - Tessent Embedded Analytics
Francisca Tan, Senior Product Manager
Siemens - Tessent Embedded Analytics
Three Ethernet Design Challenges in Industrial Automation
Key ASIC
Key ASIC
ST silicon photonics and BiCMOS technologies: the winning portfolio for AI optical interconnects
STMicroelectronics
STMicroelectronics
AI in VLSI Physical Design: Opportunities and Challenges
Japesh Kumar, Qualcomm
AI-Driven and Traditional Approaches to Accident Scenario Reconstruction
Vayavya Labs
Nitin Swamy
Vayavya Labs
From Theory to the Field: Why Side-Channel Protection Defines Post-Quantum Security
PQSecure Technologies
PQSecure Technologies
PCIe 5.0: The universal high-speed interconnect for High Bandwidth and Low Latency Applications Design Challenges & Solutions
Innosilicon Technology Ltd
Innosilicon Technology Ltd
Design Approaches and Architectures of RISC-V SoCs
Maven Silicon
Maven Silicon
Implementation of Metal ECO using Mask Programmable Cell for Hold Timing Violations
eInfochips, Inc.
Dhanyakumar Shah,Dharmik Lakhani
eInfochips, Inc.
Unlocking the Power of Digital Twins in ASICs with Adaptable eFPGA Hardware
Menta
Menta
Bridging Design Verification Gaps with Formal Verification
Karim Waseem, Si-vision
Asic Technology
Select your target foundry and technology
FPGA and eFPGA Corner
Select your target vendor and device
Today on Design And Reuse

bullet_arrow  RISC-V IP: T2M Showcases RISC-V Production IP Core Portfolio for Next-Generation SoCs at CES’26 - December 29, 2025

bullet_arrow  Challenges and Opportunities in the New Era of IoT Connectivity Opened by SGP.32 eSIM - December 26, 2025

bullet_arrow  Global Foundry 2.0 Market Revenue Surges 17% YoY in 3Q 2025 - December 24, 2025

bullet_arrow  New Role of Ethernet in AI, Automotive, and Connectivity - December 24, 2025

bullet_arrow  Nvidia stock plunges after Intel’s 18A move: what does it mean for AI chips? - December 24, 2025

bullet_arrow  Partnership Drives RISC-V Adoption in Automotive - December 24, 2025

Partner Highlight
Latest News Alerts